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fn6382 rev.0.00 page 1 of 12 december 20, 2006 fn6382 rev.0.00 december 20, 2006 isl83202 55v, 1a peak current h-bridge fet driver datasheet the isl83202 is a medium-fre quency h-bridge fet driver capable of 1a (typ) of peak dr ive current that is designed to drive high- and low-side n- channel mosfets in medium- voltage applications. optimized for pwm motor control and uninterruptible power supply systems, the isl83202 enables simple and flexible bridge-based design. with typical input- to-output propagation delays as low as 25ns and with a user- programmable dead-time r ange of 0.1s to 4.5s, the isl83202 is ideal for switchin g frequencies up to 200khz. the dead-time of the isl83202 is programmable via a single resistor. the isl83202's four independent driver control inputs (ali, ahi, bli, and b hi) allow driving of every possible switch combination except those that would cause a shoot-through condi tion. a global disable input, dis, overrides input control and ca uses the isl83202 to refresh the bootstrap capacitor whe n pulled low. integrated undervoltage protection and s hoot-through protection ensure reliable system operation. the isl83202 is available in compact 16 ld soic and 16 ld pdip packages and operates o ver the range of -55c to +125c. features ? independently drives 4 n-channel fets in half bridge or full bridge configurations ? bootstrap supply max voltage: 70vdc ? drives a 1000pf load in free air at +50c with rise and fall times of 15ns (typ) ? user-programmable dead time from 0.1 to 4.5 ? s ? dis (disable) overrides inpu t control and refreshes bootstrap capaci tor when pulled low ? input logic thresholds comp atible with 5v to 15v logic levels ? shoot-through protection ? undervoltage protection ? pb-free plus anneal available (rohs compliant) applications ? ups systems ? dc motor controls ? full bridge power supplies ? switching power amplifiers ? noise cancellation systems ? battery powered vehicles ? peripherals ? medium/large voice coil motors ? related literature - tb363, guidelines for handling and processing moisture sensitive surfac e mount devices (smds) pinout isl83202 (pdip, soic) top view ordering information part number part marking temp. range (c) package pkg. dwg. # isl83202ibz (note) 83202ibz -55 to +125 16 ld soic (n) (pb-free) m16.15 ISL83202IBZT (note) 16 ld soic (n) tape and reel (pb-free) m16.15 isl83202ipz (note) isl83202ipz -55 to +125 16 ld pdip** (pb-free) e16.3 note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/d ie attach materials and 100% matte tin plate termination finish, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ip c/ jedec j std-020. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended for use in reflow solder processing applications. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 bhb bhi bli ali del v ss dis ahi bho blo alo v dd ahs aho ahb bhs
isl83202 fn6382 rev.0.00 page 2 of 12 december 20, 2006 application block diagram functional block diagram 55v gnd load isl83202 gnd 12v ahi ali bli bhi blo bhs bho alo ahs aho 3 8 2 7 4 12 5 6 turn-on delay driver 13 level shift driver ahb ahs 9 10 11 14 15 16 1 driver turn-on delay driver turn-on delay level shift aho bhb bhs bho alo blo turn-on delay undervoltage detector v dd bhi ahi dis ali v dd del bli v ss u/v u/v
isl83202 fn6382 rev.0.00 page 3 of 12 december 20, 2006 typical application (pwm mode switching) 55v 12v 12v dis gnd gnd to optional current controller or pwm load input + - 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 bhb bhi bli ali del v ss dis ahi bho blo alo v dd ahs aho ahb bhs overcurrent latch r dis delay resistor from optional overcurrent latch r sh
isl83202 fn6382 rev.0.00 page 4 of 12 december 20, 2006 absolute maximum ratings thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 16v logic i/o voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ahs, bhs . . . . -6v (trans ient) to 65v (-55c to+150 c) voltage on ahb, bhb . . . . . . . . v ahs, bhs -0.3v to v ahs, bhs +v dd voltage on alo, blo. . . . . . . . . . . . . . . . . . v ss -0.3v to v dd +0.3v voltage on aho, bho . . . v ahs, bhs -0.3v to v ahb, bhb +0.3v input current, del . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5ma to 0ma phase slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v/ns note: all voltages are relative v ss unless otherwise specified. operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . +8.5v to +15 v voltage on v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1. 0v to +1.0v voltage on ahb, bhb . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +55v voltage on ahb, bhb . . . . . . . . v ahs, bhs +7.5v to v ahs, bhs +v dd input current, del . . . . . . . . . . . . . . . . . . . . . . . . . -4ma to -100 ? a thermal resistance ? ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 pdip package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . see curve storage temperature range . . . . . . . . . . . . . . . . . .-6 5c to +150c operating max. junction temperature. . . . . . . . . . . . . . . . . . +150c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300c (for soic - lead tips only)) *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. + 150c max junction temperature is intended for short periods of ti me to prevent shortening the lifetime. operation close to +15 0c junction may trigger the shutdown of the device even before +150c, since th is number is specified as typical. electrical specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max supply currents and under voltage protection v dd quiescent current i dd all inputs = 0v, r del = 100k 1.2 2.3 3.5 0.85 4 ma all inputs = 0v, r del = 10k 2.2 4.0 5.5 1.9 6.0 ma v dd operating current i ddo f = 50khz, no load 1.5 2.6 4.0 1.1 4.2 ma 50khz, no load, r del = 10k ? 2.5 4.0 6.4 2.1 6.6 ma ahb, bhb off qui escent current i ahbl , i bhbl ahi = bhi = 0v 0.5 1.0 1.5 0.4 1.6 ma ahb, bhb on quiescent current i ahbh , i bhbh ahi = bhi = v dd 65 145 240 40 250 ? a ahb, bhb operating current i ahbo , i bhbo f = 50khz, cl = 1000pf .65 1.1 1.8 .45 2.0 ma ahs, bhs leakage current i hlk v ahs = v bhs = 55v v ahb = v bhb = 70v v dd = not connected --1.0-- ? a v dd rising undervoltage threshold v dduv+ 6.8 7.6 8.25 6.5 8.5 v v dd falling undervoltage threshold v dduv- 6.5 7.1 7.8 6.25 8.1 v undervoltage hysteresis uvhys 0.17 0.4 0.75 0.15 0.90 v ahb, bhb undervoltage threshold vhbuv referenced to ahs and bhs 5 6 .0 7 4.5 7.5 v input pins: ali, bli, ahi, bhi, and dis low level input voltage v il full operating conditions - - 1.0 - 0.8 v high level input voltage v ih full operating conditions 2.5 - - 2.7 v input voltage hysteresis -35- - - mv low level input current i il v in = 0v, full operating conditions -145 -100 -60 -150 -50 ? a high level input current i ih v in = 5v, full operating conditions -1 - +1 -10 +10 ? a turn-on delay pin del dead time t dead r del = 100k 2.5 4.5 8.0 2.0 8.5 ? s r del = 10k 0.27 0.5 0.75 0.2 0.85 ? s
isl83202 fn6382 rev.0.00 page 5 of 12 december 20, 2006 gate driver output pins: alo, blo, aho, and bho low level output voltage v ol i out = 50ma 0.65 1.1 0.5 1.2 v high level output voltage v dd -v oh i out = -50ma 0.7 1.2 0.5 1.3 v peak pullup current i o +v out = 0v 1.0 0.6 2.0 a peak pulldown current i o -v out = 12v 1.0 0.6 2.0 a switching specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k, c l = 1000pf. parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max lower turn-off propagation delay (ali-alo, bli-blo) t lphl - 25 50 - 70 ns upper turn-off propagation delay (ahi-aho, bhi-bho) t hphl - 55 80 - 100 ns lower turn-on propagation delay (ali-alo, bli-blo) t lplh - 40 85 - 100 ns upper turn-on propagation delay (ahi-aho, bhi-bho) t hplh - 75 110 - 150 ns rise time t r -920-25ns fall time t f -920-25ns minimum input pulse width t pwin-on/off 50 - - 50 - ns output pulse response to 50ns input pulse t pwout 63 80 ns disable turn-off propagation delay (dis - lower outputs) t dislow - 50 80 - 90 ns disable turn-off propagation delay (dis - upper outputs) t dishigh - 75 100 - 125 ns disable turn-on propagation delay (dis - alo and blo) t dlplh - 40 70 - 100 ns disable turn-on propagation delay (dis- aho and bho) t dhplh r del = 10k - 1.2 2 - 3 ? s refresh pulse width (alo and blo) t ref-pw 375 580 900 350 950 ns truth table input output ali, bli ahi, bhi vdduv vhbuv dis alo, blo aho, bho xxxx1 0 0 xx1xx 0 0 0x010 0 0 1x0x0 1 0 01000 0 1 00000 0 0 note: x signifies that input c an be either a 1 or 0. electrical specifications v dd = v ahb = v bhb = 12v, v ss = v ahs = v bhs = 0v, r del = 100k (continued) parameter symbol test conditions t j = +25c t j = -55c to +150c units min typ max min max
isl83202 fn6382 rev.0.00 page 6 of 12 december 20, 2006 pin descriptions pin numbe r symbol description 1 bhb b high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstra p capacitor to this pin. 2 bhi b high-side input. logic level input that controls bho driv er (pin 16). bli (pin 3) high level input overrides bhi high le vel input to prevent half-bridge shoot-through, see truth table. di s (pin 8) high level input overrides bhi high level input. the pin can be driven by s ignal levels of 0v to 15v (no greater tha n v dd ). 3 bli b low-side input. logic level input that controls blo drive r (pin 14). if bhi (pin 2) is d riven high or not connected exte rnally then bli controls both blo and bho drivers, with dead time set by delay currents at del (pin 5). dis (pin 8) high level input overrides bli high level input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 4 ali a low-side input. logic level input that controls alo drive r (pin 13). if ahi (pin 7) is d riven high or not connected exte rnally then ali controls both alo and aho drivers, with dead time set by delay currents at del (pin 5). dis (pin 8) high level input overrides ali high level input. the pin can be driven by signal levels of 0v to 15v (no greater than v dd ). 5 del turn-on delay. connect resistor from this pin to v ss to set timing current that defines the dead time between drive rs. all drivers turn-off with no adjustable delay, so the del resistor guarantees no shoot-through by delaying the turn-on of all drivers. the voltage across the del resistor is approximately v dd -2v. 6v ss chip negative supply, generally will be ground. 7 ahi a high-side input. logic level input that controls aho driv er (pin 10). ali (pin 4) high level input overrides ahi high le vel input to prevent half-bridge shoot-through, see truth table. di s (pin 8) high level input overrides ahi high level input. the pin can be driven by s ignal levels of 0v to 15v (no greater tha n v dd ). 8 dis disable input. logic level input that when taken high sets all four outputs low. dis high overrides all other inputs. when dis is taken low the outputs are controlled by the other inputs . the pin can be driven by si gnal levels of 0v to 15v (no greater than v dd ). 9 ahb a high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of bootstrap diode and positive side of bootstra p capacitor to this pin. 10 aho a high-side output. connect to gate of a high-side power m osfet. 11 ahs a high-side source connection. connect to source of a high -side power mosfet. connect negative side of bootstrap capacitor to this pin. 12 v dd positive supply to control logi c and lower gate drivers. de-cou ple this pin to v ss (pin 6). 13 alo a low-side output. connect to gate of a low-side power mos fet. 14 blo b low-side output. connect to gate of b low-side power mos fet. 15 bhs b high-side source connection. connect to source of b high -side power mosfet. connect negative side of bootstrap capacitor to this pin. 16 bho b high-side output. connect to gate of b high-side power m osfet.
isl83202 fn6382 rev.0.00 page 7 of 12 december 20, 2006 timing diagrams figure 1. independent mode figure 2. bistate mode figure 3. disable function dis=0 xli xhi xlo xho t lphl t hphl t hplh t lplh t r (10% - 90%) t f (10% - 90%) x = a or b, a and b halves of bri dge controller are independent and uv dis=0 xli xhi = hi or not connected xlo xho and uv dis or uv xli xhi xlo xho t dlplh t dis t dhplh t ref-pw
isl83202 fn6382 rev.0.00 page 8 of 12 december 20, 2006 performance curves figure 4. i dd supply current vs temperature and v dd supply voltage figure 5. v dd supply current vs temperature and switching frequency (1000pf load) figure 6. floating (ixhb) bias current vs frequency and load figure 7. gate source/sink peak current vs bias supply voltage at +25c figure 8. gate current vs temperature, normalized to +25c figure 9. v dd -v oh vs bias voltage temperature -60 -40 -20 0 20 40 60 80 100 120 140 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 junction temperature (c) i dd supply current (ma) v dd = 16v v dd = 15v v dd = 12v v dd = 10v v dd = 8v -60 -40 -20 0 20 40 60 80 100 120 140 4 5 6 7 8 9 10 11 12 13 14 15 16 junction temperature (c) i dd supply current (ma) 200khz 100khz 50khz 10khz 0 50 100 150 200 0 1 2 3 4 5 6 7 8 frequency (khz) loaded, nl bias currents (ma) 1000pf load no load 8 9 10 11 12 13 14 15 0.5 0.75 1 1.25 1.5 1.75 bias supply voltage (v) at +25c peak gate current (a) bias 2 source and sink -75 -50 -25 0 25 50 75 100 125 150 0.8 0.9 1 1.1 1.2 junction temperature (c) normalized gate sink/source current (a) 8 9 10 11 12 13 14 15 0.6 1 1.4 v dd supply voltage (v) v dd -v oh (v) 1.2 0.8 -55c -40c 0c +25 c +125c +150c
isl83202 fn6382 rev.0.00 page 9 of 12 december 20, 2006 figure 10. v ol vs bias voltage and temperature figure 11. undervoltage trip vol tages vs temperature figure 12. upper lower turn-on / turn-off propagation delay vs temperature figure 13. upper/lower dis(able) to turn-on/off vs temperature (c) figure 14. full bridge level-shift current vs frequency (khz) figure 15. maximum power dissipation vs ambient temperature performance curves (continued) 8 9 10 11 12 13 14 1.4 v dd supply voltage (v) v ol (v) 15 1.2 0.8 0.6 -55c -40c 0c +25c +125c +150c 1 -60 -40 -20 0 20 40 60 80 100 120 140 160 5 5.5 6 6.5 7 7.5 8 junction temperature (c) v dd , bias supply voltage (v) lower u/v reset lower u/v set upper u/v set/reset -60 -40 -20 0 20 40 60 80 100 120 140 160 20 30 40 50 60 70 80 90 100 junction temperature (c) propagation delays (ns) upper t on upper t off lower t on lower t off -60 -40 -20 0 20 40 60 80 100 120 140 160 10 100 10 4 junction temperature (c) dis to turn-on/off time (ns) 1000 dishton dishtoff dislton disloff 0 20 40 60 80 100 0.5 1 1.5 2 switching frequency (khz) level-shift current (ma) -60 -30 0 30 60 90 120 150 0 0.5 1 1.5 2 2.5 ambient temperature (c) total power dissipation (w) soic 16 pin dip quiescent bias component
isl83202 fn6382 rev.0.00 page 10 of 12 december 20, 2006 figure 16. dead-time vs del resistance and bias supply (v dd ) voltage performance curves (continued) 0 10 20 30 40 50 60 70 80 90 100 100 1000 10 4 dead time resistance (k ? ) dead time (ns) v dd = 12v v dd = 9v v dd = 15v
isl83202 fn6382 rev.0.00 page 11 of 12 december 20, 2006 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between eng lish and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated i n je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrus ions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not i nclude dambar protrusions. damb ar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1. 14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a- 0.210 - 5.33 4 a1 0.015 - 0.39 -4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 -5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
fn6382 rev.0.00 page 12 of 12 december 20, 2006 isl83202 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 ? 0 8 0 8 - rev. 1 6/05

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